(1) Field of the Invention
The invention relates to the fabrication of integrated circuit devices, and more particularly, to a method for the creation of a reliable top metal fuse.
(2) Description of the Prior Art
Increased semiconductor device performance has over the years been achieved by decreasing device dimensions and by increasing device packaging densities. The therefrom following sharp reductions in device feature size imposes increasingly strict limitations on the technologies that are used for semiconductor device creation. Increasing device density requires the creation of more complex networks of interconnect traces over a surface in which multiple active semiconductor devices have previously been created, a requirement that is typically addressed by increasing the number of overlying layers of electrical interconnect wiring. It is in this respect not uncommon to use from two to six overlying layers of conductive interconnects, these layers of interconnects are embedded in layers of insulating material such as layers of Intra Level Dielectric (ILD) and Inter Metal Dielectric (IMD). After these layers of interconnect have been created, a passivation layer is generally deposited over the surface of the upper layer of insulation for the protection of the underlying semiconductor devices and the network of conductive interconnects.
In addition to the above referred to active semiconductor devices that are provided over for instance the surface of a silicon substrate, semiconductor constructs frequently are also provided with means of further personalizing these devices by providing one or more fuses as part of the device.
With the increased number of overlying layers of insulation and with the reduction in device feature size, the conventional approach of creating a poly fuse, that is accessed via an opening created through the layers of insulation, becomes less attractive and has therefore been replaced with the creation of metal fuses.
Laser technology is typically and most beneficially used for the opening to the fuse for purposes of device personalization. These layers are, aligned with the fuse point of contact, penetrated, creating an opening through these layers that aligns with the fuse point of contact, whereby however a fraction of these layers remains in place over a height above the fuse point of contact. This layer overlying the fuse point of contact has as a design requirement that the layer remains a solid layer of consistent layer density, that is no cracks or other density disturbances are allowed in the fraction of the layer of insulation that remains in place overlying the fuse point of contact. The laser technology that is used for opening (or blowing) the fuse combined with the characteristics of the typically used low-K dielectrics that are used for the layers of insulation, readily and frequently lead to the occurrence of cracks in the remaining overlying layer of insulation, leading to increased product loss.
An additional concern is the complexity of the process that is required in order to create the layers of interconnect traces in combination with electrical fuse capability. It is not uncommon to have a process requiring four steps of photoresist mask processing, each step in addition requiring relatively extensive steps of surface clean after the patterned layers of photoresist have been removed prior to additional processing steps.
Concurrent with the creation of access to a fuse, openings are frequently created through the layers of insulation to a bond pad, which is a point of contact in the surface of the layers of insulating material. The non-exposed surface of the created bond pad remains covered with a layer of insulating material. Good adhesion is required in this interface between the bond pad and the partially overlying layer of insulating material for reasons of device performance of which most notably can be cited requirements of leakage currents from the bond pad to surrounding areas and contact resistance to the bond pad.
The invention addresses these and other concerns by providing a sequence of processing steps for the creation of a fuse opening and a contact pad, also referred to as bond pad, through layers of passivation, whereby negative effects that are typically experienced due to the presence of low-K dielectric overlying the fuse are eliminated.
U.S. Pat. No. 6,162,686 (Huang et al.) shows a fuse opening process and passivation process.
U.S. Pat. No. 5,985,765 (Hsiao et al.) shows integrated BP and fuse process.
U.S. Pat. No. 6,235,557 B1 (Manley) shows a fuse, top metal and passivation process.
U.S. Pat. No. 6,054,340 (Mitchell et al.) discloses another fuse and passivation process.